The present invention relates to the field of data transmission, and, more particularly, to clock signal generation during data transmission.
Data may be exchanged between devices over a serial bus according to a USB (user serial bus) type protocol. According to this protocol, the USB clock signal is not transmitted on the bus. Only some synchronization bits are sent at the beginning of transmission so that the devices connected to this bus can get synchronized, to send or receive data, on this bus. In systems using a data transmission protocol of this kind, the integrated circuits usually include a circuit for the generation of a synchronous clock signal based on a phase-locked loop and a quartz crystal.
The invention is concerned with a system comprising smart-card type portable carriers. Portable carriers of this kind cannot incorporate a circuit for the generation of a prior art synchronized clock signal because it is not possible to integrate either the quartz or the phase-locked loop therein, as these elements take up a great deal of space.
The invention therefore relates to a device for the regeneration of the clock signal of the bus, from a few external synchronization pulses, at least two of them. In the example of a USB serial bus, the regeneration of a USB clock signal must have high precision, in the range of 1%.
According to the invention, an internal oscillator is used, giving an internal frequency clock signal. This clock signal is used as a reference signal for the regeneration of the USB clock signal.
An object of the invention is to compute the number of reference clock signal pulses between the first two synchronization pulses sent on the USB bus at the start of each transaction. Thus, a rough measurement is obtained of the period of the USB clock signal. Furthermore, to ensure the synchronization and precision of the internally regenerated USB clock signal, the delay of each of these two synchronization pulses with reference to the immediately preceding pulse of the reference clock signal is measured. This delay is computed with reference to a time unit defined internally. From the measurement of these two delays and the measurement of the number of reference clock signal periods, it is possible to achieve a precise computation of the period of the USB clock signal and regenerate this USB clock signal synchronously.
The invention therefore relates to a device for the regeneration of a clock signal from at least two synchronization pulses transmitted on an external serial bus in an integrated circuit comprising an internal oscillator capable of giving a reference clock signal. The device preferably defines the time unit and provides a fine measurement, in the time unit, of the delay of two synchronization pulses each with respect to a preceding pulse of the reference clock signal. The device has a measurement of the reference clock signal period in the time unit available and further includes circuitry to measure the number of reference clock signal strokes between the two synchronization pulses. The measurements of delay, of the reference clock signal period and of the number of clock signal strokes being applied as starting data elements for a computation unit capable of computing the corresponding period and of initializing a countdown unit activated at each regeneration cycle to give a regenerated clock signal pulse at output.